Performance Evaluation of a Low Energy Universal Gate for VLSI with 16nm Technology
DOI:
https://doi.org/10.56286/ntujet.v1i3.209Keywords:
gate, VSLI, NAND, CMOS, DELAY, LOGICAbstract
NAND & NOR logic gates are general purpose logic gates that can be used to build other logic gates. This article describes a new NAND gate based on 3T (3 transistors) which has the correct output logic level and behaves similarly to the previous design NAND gate logic. The proposed structure has faster processing and lower power consumptionwhat makes it ideal for large-scale integration (VLSI) applications. Typical 16nm CMOS fabrication techniques were used for simulation, building Nand Gate, and to compare it to Nand Gate with different techniques and design such as using four transistors. It turns out that the amount of delay in this desgin with the selected technology compared to other projects with other technologies is less, that is, 0.02966 ns, which proves that the smaller the delay, the faster the gate operates.
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